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rev.2.00 jun. 28, 2004 page 1 of 13 hd74lv595a 8-bit shift registers with 3-state outputs rej03d0335?0200z (previous ade-205-281 (z)) rev.2.00 jun. 28, 2004 description this device each contains an 8-bi t serial-in, parallel-out shift registers that feeds an 8-bit d-type storage register. the storage register has parallel 3-state outputs. separate clocks are provided for both the shift register and the storage register. the shift register has a di rect-overriding clear, serial input, an d serial output pins for cascading. both the shift register and the storage register clocks are positive-edge triggered. if the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storag e register. low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. features ? v cc = 2.0 v to 5.5 v operation ? all inputs v ih (max.) = 5.5 v (@v cc = 0 v to 5.5 v) ? all outputs v o (max.) = 5.5 v (@v cc = 0 v) ? typical v ol ground bounce < 0.8 v (@v cc = 3.3 v, ta = 25c) ? typical v oh undershoot > 2.3 v (@v cc = 3.3 v, ta = 25c) ? output current 6 ma (@v cc = 3.0 v to 3.6 v), 12 ma (@v cc = 4.5 v to 5.5 v) ? ordering information part name package type package code package abbreviation taping abbreviation (quantity) hd74lv595afpel sop?16 pin (jeita) fp?16dav fp el (2,000 pcs/reel) hd74lv595arpel sop?16 pin (jedec) fp?16dnv rp el (2,500 pcs/reel) HD74LV595ATELL tssop?16 pin ttp?16dav t ell (2,000 pcs/reel) note: please consult the sales office for the above package availability. function table inputs ser srclk srclr rclk g function xxxxhforce outputs into high-im pedance state xxxxl enable parallel output x x l x x reset shift register l h x x shift data into shift register h h x x shift data into shift register x h x x shift register remains unchanged xxx x transfer shift register contents to latch register xxx x latch register remains unchanged note: h: high level l: low level x: immaterial : low to high transition : high to low transition
hd74lv595a rev.2.00 jun. 28, 2004 page 2 of 13 pin arrangement 13 14 11 12 15 16 9 10 v cc q a ser g rclk srclk 1 2 3 4 5 6 7 8 q b q c q d q e q f q g q h gnd srcl r q h' (top view) absolute maximum ratings item symbol ratings unit conditions supply voltage range v cc ?0.5 to 7.0 v input voltage range* 1 v i ?0.5 to 7.0 v ?0.5 to v cc + 0.5 output: h or l output voltage range* 1, 2 v o ?0.5 to 7.0 v output: z or v cc : off input clamp current i ik ?20 ma v i < 0 output clamp current i ok 50 ma v o < 0 or v o > v cc continuous output current i o 25 ma v o = 0 to v cc continuous current through v cc or gnd i cc or i gnd 70 ma 785 sop maximum power dissipation at ta = 25c (in still air)* 3 p t 500 mw tssop storage temperature tstg ?65 to 150 c notes: the absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. the input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. this value is limited to 5.5 v maximum. 3. the maximum package power dissipation was calculated using a junction temperature of 150c.
hd74lv595a rev.2.00 jun. 28, 2004 page 3 of 13 recommended operating conditions item symbol min max unit conditions supply voltage range v cc 2.0 5.5 v input voltage range v i 05.5v 0v cc h or l output voltage range v o 05.5 v high impedance state ? ?50 av cc = 2.0 v ??2 v cc = 2.3 to 2.7 v ??6 v cc = 3.0 to 3.6 v i oh ? ?12 ma v cc = 4.5 to 5.5 v ?50 av cc = 2.0 v ?2 v cc = 2.3 to 2.7 v ?6 v cc = 3.0 to 3.6 v output current i ol ?12 ma v cc = 4.5 to 5.5 v 0 200 v cc = 2.3 to 2.7 v 0 100 v cc = 3.0 to 3.6 v input transition rise or fall rate ? t / ? v 020 ns/v v cc = 4.5 to 5.5 v operating free-air temperature ta ?40 85 c note: unused or floating inputs must be held high or low.
hd74lv595a rev.2.00 jun. 28, 2004 page 4 of 13 logic diagram g rclk (13) (12) (10) (11) (14) (15) srclr srclk ser 1d r c1 3r 3s c3 2r 2s r c2 3r 3s c3 2r 2s r c2 3r 3s c3 2r 2s r c2 3r 3s c3 2r 2s r c2 3r 3s c3 2r 2s r c2 3r 3s c3 2r 2s r c2 3r 3s c3 2r 2s r c2 3r 3s c3 q a (1) q b (2) q c (3) q d (4) q e (5) q f (6) q g (7) q h (9) q h '
hd74lv595a rev.2.00 jun. 28, 2004 page 5 of 13 timing diagram srclk ser rclk q a q b q c q d q e q f q g q h q h' s rclr g high impedance clear shift dc electrical characteristics ta = ?40 to 85c item symbol v cc (v) min typ max unit test conditions 2.0 1.5 ? ? 2.3 to 2.7 v cc 0.7 ? ? 3.0 to 3.6 v cc 0.7 ? ? v ih 4.5 to 5.5 v cc 0.7 ? ? 2.0 ? ? 0.5 2.3 to 2.7 ? ? v cc 0.3 3.0 to 3.6 ? ? v cc 0.3 input voltage v il 4.5 to 5.5 ? ? v cc 0.3 v min to max v cc ? 0.1 ? ? i oh = ?50 a 2.3 2.0 ? ? i oh = ?2 ma 3.0 2.48 ? ? i oh = ?6 ma v oh 4.5 3.8 ? ? i oh = ?12 ma min to max ? ? 0.1 i ol = 50 a 2.3 ? ? 0.4 i ol = 2 ma 3.0 ? ? 0.44 i ol = 6 ma output voltage v ol 4.5 ? ? 0.55 v i ol = 12 ma input current i in 0 to 5.5 ? ? 1 av in = 5.5 v or gnd off-state output current i oz 5.5 ? ? 5 av o = v cc or gnd quiescent supply current i cc 5.5 ? ? 20 av in = v cc or gnd, i o = 0 output leakage current i off 0??5 av i or v o = 0 to 5.5 v input capacitance c in 3.3 ? 3.5 ? pf v i = v cc or gnd note: for conditions shown as min or max, use the appr opriate values under recommended operating conditions.
hd74lv595a rev.2.00 jun. 28, 2004 page 6 of 13 switching characteristics v cc = 2.5 0.2 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) 65 80 ? 45 ? c l = 15 pf maximum clock frequency f max 60 70 ? 40 ? mhz c l = 50 pf ? 11.6 16.4 1.0 19.5 c l = 15 pf ? 14.8 19.4 1.0 22.5 c l = 50 pf srclk q h ' ? 10.5 15.3 1.0 18.0 c l = 15 pf t plh /t phl ? 13.7 18.3 1.0 21.0 c l = 50 pf rclk q a ? q h ? 11.2 16.2 1.0 18.2 c l = 15 pf propagation delay time t phl ? 14.4 19.2 1.0 21.2 ns c l = 50 pf srclk q h ' ? 10.3 14.8 1.0 17.5 c l = 15 pf enable time t zh t zl ? 12.2 17.7 1.0 20.5 ns c l = 50 pf ? 7.6 11.5 1.0 13.5 c l = 15 pf disable time t hz t lz ? 14.4 18.2 1.0 19.2 ns c l = 50 pf g q a ? q h 5.5 ? ? 5.5 ? ser before srclk 10.0 ? ? 10.5 ? srclk before rclk 10.0 ? ? 11.0 ? srclr low before rclk setup time t su 5.0 ? ? 5.0 ? ns srclr high (inactive) before srclk 2.0 ? ? 2.0 ? ser after srclk 0.5 ? ? 0.5 ? srclk after rclk hold time t h 0.5 ? ? 0.5 ? ns srclr low after rclk 7.0 ? ? 7.5 ? rclk high or low 7.0 ? ? 7.5 ? srclk high or low pulse width t w 6.0 ? ? 6.5 ? ns srclr low
hd74lv595a rev.2.00 jun. 28, 2004 page 7 of 13 switching characteristics (cont) v cc = 3.3 0.3 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) 80 150 ? 70 ? c l = 15 pf maximum clock frequency f max 55 130 ? 50 ? mhz c l = 50 pf ? 8.8 13.0 1.0 15.0 c l = 15 pf ? 11.3 16.5 1.0 18.5 c l = 50 pf srclk q h ' ? 7.7 11.9 1.0 13.5 c l = 15 pf t plh /t phl ? 10.2 15.4 1.0 17.0 c l = 50 pf rclk q a ? q h ? 8.4 12.8 1.0 13.7 c l = 15 pf propagation delay time t phl ? 10.9 16.3 1.0 17.2 ns c l = 50 pf srclk q h ' ? 7.5 11.5 1.0 13.5 c l = 15 pf enable time t zh t zl ? 9.0 15.0 1.0 17.0 ns c l = 50 pf ? 5.9 11.7 1.0 13.5 c l = 15 pf disable time t hz t lz ? 12.1 15.7 1.0 16.2 ns c l = 50 pf g q a ? q h 3.5 ? ? 3.5 ? ser before srclk 8.0 ? ? 8.5 ? srclk before rclk 8.0 ? ? 9.0 ? srclr low before rclk setup time t su 3.0 ? ? 3.0 ? ns srclr high (inactive) before srclk 1.5 ? ? 1.5 ? ser after srclk 0.0 ? ? 0.0 ? srclk after rclk hold time t h 0.0 ? ? 0.0 ? ns srclr low after rclk 5.0 ? ? 5.0 ? rclk high or low 5.0 ? ? 5.0 ? srclk high or low pulse width t w 5.0 ? ? 5.0 ? ns srclr low
hd74lv595a rev.2.00 jun. 28, 2004 page 8 of 13 switching characteristics (cont) v cc = 5.0 0.5 v ta = 25c ta = ?40 to 85c item symbol min typ max min max unit test conditions from (input) to (output) 135 185 ? 115 ? c l = 15 pf maximum lock frequency f max 95 155 ? 85 ? mhz c l = 50 pf ? 6.2 8.2 1.0 9.4 c l = 15 pf ? 7.7 10.2 1.0 11.4 c l = 50 pf srclk q h ' ? 5.4 7.4 1.0 8.5 c l = 15 pf t plh /t phl ? 6.9 9.4 1.0 10.5 c l = 50 pf rclk q a ? q h ? 5.9 8.0 1.0 9.1 c l = 15 pf propagation delay time t phl ? 7.4 10.0 1.0 11.1 ns c l = 50 pf srclk q h ' ? 4.8 8.6 1.0 10.0 c l = 15 pf enable time t zh t zl ? 8.3 10.6 1.0 12.0 ns c l = 50 pf ? 4.8 8.6 1.0 10.0 c l = 15 pf disable time t hz t lz ? 7.6 11.0 1.0 11.0 ns c l = 50 pf g q a ? q h 3.0 ? ? 3.0 ? ser before srclk 5.0 ? ? 5.0 ? srclk before rclk 5.0 ? ? 5.0 ? srclr low before rclk setup time t su 2.5 ? ? 2.5 ? ns srclr high (inactive) before srclk 2.0 ? ? 2.0 ? ser after srclk 0.0 ? ? 0.0 ? srclk after rclk hold time t h 0.0 ? ? 0.0 ? ns srclr low after rclk 5.0 ? ? 5.0 ? rclk high or low 5.0 ? ? 5.0 ? srclk high or low pulse width t w 5.0 ? ? 5.0 ? ns srclr low output-skew characteristics c l = 50 pf ta = 25c ta = ?40 to 85c item symbol v cc = (v) min max min max unit 2.3 to 2.7 ? 2.0 ? 2.0 3.0 to 3.6 ? 1.5 ? 1.5 output skew t sk (o) 4.5 to 5.5 ? 1.0 ? 1.0 ns note: skew between any outputs of the same package switchi ng in the same direction. this parameter is warranted but not production tested.
hd74lv595a rev.2.00 jun. 28, 2004 page 9 of 13 operating characteristics c l = 50 pf ta = 25c item symbol v cc = (v) min typ max unit test conditions 3.3 ? 32.7 ? power dissipation capacitance c pd 5.0 ? 33.1 ? pf f = 10 mhz noise characteristics c l = 50 pf ta = 25c item symbol v cc = (v) min typ max unit test conditions quiet output, maximum dynamic v ol v ol (p) 3.3 ? 0.65 0.8 v quiet output, minimum dynamic v ol v ol (v) 3.3 ? ?0.59 ?0.8 v quiet output, minimum dynamic v oh v oh (v) 3.3 ? 2.84 ? v high-level dynamic input voltage v ih (d) 3.3 2.31 ? ? v low-level dynamic input voltage v il (d) 3.3 ? ? 0.99 v test circuit open gnd c 1 k ? v cc v cc s2 l output test s2 t / t plh phl open gnd t / t zh hz t / t zl lz note: c includes the probe and jig capacitance. l
hd74lv595a rev.2.00 jun. 28, 2004 page 10 of 13 t r t f 90% 90% 10% 10% 50% v cc 50% v cc srclk waveform ? 1 waveform ? 2 waveform ? 3 q h' v cc gnd t w 1/f max t plh t tlh t thl t phl v cc gnd v cc gnd t w 50% v cc 50% v cc 50% v cc srclr srclk q h' t phl t su v cc gnd 50% v cc 50% v cc t plh /t phl rclk q a -q h
hd74lv595a rev.2.00 jun. 28, 2004 page 11 of 13 v oh v ol cc 50 % v cc 50 % v t r t f t zl 0 v 0 v v cc v cc t lz t zh t hz 10 % 10 % 90 % 90 % cc 50 % v cc 50 % v g waveform ? a waveform ? 4 waveform ? 5 waveform ? 6 waveform ? b v ? 0.3 v oh v + 0.3 v ol 50% v cc 50% v cc v cc gnd v cc gnd ser srclk valid t su t h v cc gnd v cc gnd srclk rclk 50% v cc 50% v cc t w t su 1. input waveform: prr 1 mhz, zo = 50 ? , t 3 ns, t 3 ns 2. waveform ? a is for an output with internal conditions such that the output is low except when disabled by the output control. 3. waveform ? b is for an output with internal conditions such that the output is high except when disabled by the output control. 4. the output are measured one at a time with one transition per measurement. notes:
hd74lv595a rev.2.00 jun. 28, 2004 page 12 of 13 package dimensions package code jedec jeita mass (reference value) fp-16dav ? conforms 0.24 g *ni/pd/au plating *0.20 0.05 *0.40 0.06 0.12 0.15 m 2.20 max 5.5 10.06 0.80 max 16 9 1 8 10.5 max + 0.20 ? 0.30 7.80 0.70 0.20 0 ? ? 8 ? 0.10 0.10 1.15 1.27 as of january, 2003 unit: mm package code jedec jeita mass (reference value) fp-16dnv conforms conforms 0.15 g *ni/pd/au plating 1.27 16 9 1 8 0.15 0.25 m 1.75 max 3.95 *0.20 0.05 9.9 0 ? ? 8 ? 10.3 max + 0.10 ? 0.30 6.10 + 0.67 ? 0.20 0.60 + 0.11 ? 0.04 0.14 *0.40 0.06 0.635 max 1.08 as of january, 2003 unit: mm
hd74lv595a rev.2.00 jun. 28, 2004 page 13 of 13 package code jedec jeita mass (reference value) ttp-16dav ? ? 0.05 g *ni/pd/au plating 0.50 0.10 0? ? 8? *0.15 0.05 6.40 0.20 0.10 1.10 max 0.13 m 0.65 18 16 9 4.40 5.00 5.30 max 0.07 +0.03 ?0.04 0.65 max 1.0 * 0.20 0.05 as of january, 2003 unit: mm
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